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LTC1960 Dual Battery Charger/ Selector with SPI Interface
FEATURES
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DESCRIPTIO
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s s s
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s s s
Complete Dual-Battery Charger/Selector System Serial SPI Interface Allows External C Control and Monitoring Simultaneous Dual-Battery Discharge Extends Run Time by Typically 10% Simultaneous Dual-Battery Charging Reduces Charging Time by up to 50% Automatic PowerPathTM Switching in <10s Prevents Power Interruption Available in a 36-Pin Narrow SSOP Package Circuit Breaker Protects Against Overcurrent Faults 5% Accurate Adapter Current Limit Maximizes Charging Rate* 95% Efficient Synchronous Buck Charger Charger has Low 0.5V Dropout Voltage No Audible Noise Generation, even with Ceramic Capacitors 11-Bit VDAC Delivers 0.8% Voltage Accuracy 10-Bit IDAC Delivers 5% Current Accuracy VIN up to 32V; VBATT up to 28V
The LTC(R)1960 is a highly-integrated battery charger and selector intended for portable products using dual smart batteries. A serial SPI interface allows an external microcontroller to control and monitor status of both batteries. A proprietary PowerPath architecture supports simultaneous charging or discharging of both batteries. Typical battery run times are extended by 10%, while charging times are reduced by up to 50%. The LTC1960 automatically switches between power sources in less than 10s to prevent power interruption upon battery or wall adapter removal. The synchronous buck battery charger delivers 95% efficiency with only 0.5V dropout voltage, and prevents audible noise in all operating modes. Patented* input current limiting with 5% accuracy charges batteries in the shortest possible time without overloading the wall adapter. The LTC1960's 36-pin narrow SSOP package allows implementation of a complete SBS-compliant dual battery system while consuming minimum PCB area.
, LTC and LT are registered trademarks of Linear Technology Corporation. PowerPath is a trademark of Linear Technology Corporation. *U.S. Patent No. 5,723,970
APPLICATIO S
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Portable Computers Portable Instruments
TYPICAL APPLICATIO
LTC1960 Dual Battery/Selector System Architecture
DC IN
SYSTEM POWER
LTC1960 4 SPI BAT2 BAT1
MICROCONTROLLER
SMBus
3500 3000 2500 2000 1500 1000 500 0 3500 3000 2500 2000 1500 1000 500 0 0
BATTERY CURRENT (mA)
1960 TA01
U
Dual vs Sequential Charging
BAT1 CURRENT BAT2 CURRENT SEQUENTIAL BAT1 CURRENT BAT2 CURRENT DUAL 100 MINUTES 50 100 150 200 TIME (MINUTES) 250 300 BATTERY TYPE: 10.8V Li-Ion (MOLTECH NI2020) REQUESTED CURRENT = 3A REQUESTED VOLTAGE = 12.3V MAX CHARGER CURRENT = 4.1A 1960 G10
1960f
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1
LTC1960
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW VPLUS BAT2 BAT1 SCN SCP GDCO GDCI GB1O GB1I 1 2 3 4 5 6 7 8 9 36 SCH2 35 GCH2 34 GCH1 33 SCH1 32 TGATE 31 BOOST 30 SW 29 DCIN 28 VCC 27 BGATE 26 PGND 25 COMP1 24 CLP 23 CSP 22 CSN 21 MOSI 20 MISO 19 SCK G PACKAGE 36-LEAD PLASTIC SSOP
TJMAX = 125C, JA = 85C/W
Voltage from DCIN, SCP, SCN, CLP, VPLUS, SW to GND ................................................32V to - 0.3V Voltage from SCH1, SCH2 to GND .............28V to - 0.3V Voltage from BOOST to GND .....................41V to - 0.3V PGND with Respect to GND .................................. 0.3V CSP, CSN, BAT1, BAT2 to GND ....................28V to - 5V LOPWR, DCDIV to GND .............................10V to - 0.3V SSB, SCK, MOSI, MISO to GND ................... 7V to -0.3V COMP1 to GND ............................................ 5V to -0.3V Operating Ambient Temperature Range (Note 7) ........................................ 0C to 70C Operating Junction Temperature .......... - 40C to 125C Storage Temperature ............................ - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1960CG
GB2O 10 GB2I 11 LOPWR 12 VSET 13 ITH 14 ISET 15 GND 16 DCDIV 17 SSB 18
Consult LTC marketing for parts specified with wider operating temperature ranges.
The q denotes specifications which apply over the full operating temperature range (Note 7), otherwise specifications are at TA = 25C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V unless otherwise noted.
SYMBOL PARAMETER DCIN Operating Range ICH DCIN Operating Current Battery Operating Voltage Range Battery Drain Current VFDC VFB1 VFB2 VFSCN UVLO UVHYS VVCC VLDR VPLUS Diodes Forward Voltage: DCIN to VPLUS BAT1 to VPLUS BAT2 to VPLUS SCN to VPLUS Undervoltage Lockout Threshold UV Lockout Hysteresis VCC Regulator Output Voltage VCC Load Regulation IVCC = 0mA to 10mA CONDITIONS DCIN Selected Not Charging (DCIN Selected) Charging (DCIN Selected) Battery Selected, PowerPath Function (Note 2) Battery Selected, Not Charging, VDCIN = 0V IVCC = 10mA IVCC = 0mA IVCC = 0mA IVCC = 0mA VPLUS Ramping Down, Measured at VPLUS to GND VPLUS Rising, Measured at VPLUS to GND 5
q
ELECTRICAL CHARACTERISTICS
MIN 6
TYP
MAX 28
UNITS V mA mA V A V V V V
Supply and Reference 1 1.3 6 175 0.8 0.7 0.7 0.7 3 3.5 60 5.2 0.2 5.4 1 3.9 1.5 2 28
2
U
V mV V %
1960f
W
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WW
W
LTC1960
The q denotes specifications which apply over the full operating temperature range (Note 7), otherwise specifications are at TA = 25C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V unless otherwise noted.
SYMBOL VTOL ITOL f0SC fDO DCMAX IMAX ISNS CMSL CMSH VCL1 TG tr TG tf BG tr BG tf Trip Points VTR VTHYS IBVT VTSC VFTO VOVSD DACs IRES tIP tILOW VRES VSTEP VOFF tVP IDAC Resolution IDAC Pulse Period: Normal Mode Low Current Mode VDAC Resolution VDAC Granularity VDAC Offset VDAC Pulse Period (Note 6) 7 Guaranteed Monotonic (5V < VBAT < 25V) Guaranteed Monotonic Above IMAX/16 10 6 11 16 0.8 11 16.5 10 50 15 bits s ms bits mV V s DCDIV/LOPWR Threshold DCDIV/LOPWR Hysteresis Voltage DCDIV/LOPWR Input Bias Current Short-Circuit Comparator Threshold Fast Power Path Turn-Off Threshold Overvoltage Shutdown Threshold as a Percent of Programmed Charger Voltage VDCDIV or VLOPWR Falling VDCDIV or VLOPWR Rising VDCDIV or VLOPWR = 1.19V VSCP - VSCN, VCC 5V VDCDIV Rising from VCC VSET Rising from 0.8V until TGATE and BGATE Stop Switching
q q
ELECTRICAL CHARACTERISTICS
PARAMETER Overall Voltage Accuracy Overall Current Accuracy Regulator Switching Frequency Regulator Switching Frequency in Low Dropout Mode Regulator Maximum Duty Cycle Maximum Current Sense Threshold CA1 Input Bias Current CA1/I1 Input Common Mode Low CA1/I1 Input Common Mode High CL1 Turn-On Threshold TGATE Transition Time: TGATE Rise Time TGATE Fall Time BGATE Transition Time: BGATE Rise Time BGATE Fall Time
CONDITIONS 5V VOUT < 25V, (Note 3)
q
MIN -0.8 -1 -5 -6 255
TYP
MAX 0.8 1 5 6
UNITS % % % % kHz kHz %
Switching Regulator
IDAC Value = 3FFHEX VCSP, VCSN = 12V Duty Cycle 99%
q
300 25 99.5 155 150
345
20 99
VITH = 2.2V VCSP = VCSN > 5V
140 0
190
mV A V
VDCIN-0.2 95 CLOAD = 3300pF, 10% to 90% CLOAD = 3300pF, 10% to 90% CLOAD = 3300pF, 10% to 90% CLOAD = 3300pF, 10% to 90% 1.166 100 50 50 50 40 1.19 30 20 90 6 100 7 107 200 115 7.9 105 90 90 90 80 1.215
V mV ns ns ns ns V mV nA mV V %
1960f
3
LTC1960
The q denotes specifications which apply over the full operating temperature range (Note 7), otherwise specifications are at TA = 25C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V unless otherwise noted.
SYMBOL tONC tOFFC VCON PARAMETER GCH1/GCH2 Turn-On Time GCH1/GCH2 Turn-Off Time CH Gate Clamp Voltage GCH1 GCH2 CH Gate Off Voltage GCH1 GCH2 CH Switch Reverse Turn-Off Voltage GCH1/GCH2 Active Regulation: Max Source Current Max Sink Current BATX Voltage Below Which Charging is Inhibited (Does Not Apply to Low Current Mode) Blanking Period after UVLO Trip Blanking Period after LOPWR Trip GB1O/GB2O/GDCO Turn-On Time GB1O/GB2O/GDCO Turn-Off Time Output Gate Clamp Voltage GB1O GB2O GDCO Output Gate Off Voltage GB1O GB2O GDCO PowerPath Switch Reverse Turn-Off Voltage PowerPath Switch Forward Regulation Voltage GDCI/GB1I/GB2I Active Regulation Source Current Sink Current Switches Held Off Switches in 3-Diode Mode VGS < -3V, from Time of Battery/DC Removal, or LOPWR Indication VGS > -1V, from Time of Battery/DC Removal, or LOPWR Indication ILOAD = 1A Highest (VBAT1 or VSCP) - VGB1O Highest (VBAT2 or VSCP) - VGB2O Highest (VDCIN or VSCP) - VGDCO ILOAD = -25A Highest (VBAT1 or VSCP) - VGB1O Highest (VBAT2 or VSCP) - VGB2O Highest (VDCIN or VSCP) - VGDCO VSCP - VBATX or VSCP - VDCIN 6V VSCP 28V VBATX - VSCP or VDCIN - VSCP 6V VSCP 28V (Note 4) -4 75 A A
q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS VGCHX - VSCHX > 3V, VSCHX = TBD, CLOAD = 3nF VGCHX - VSCHX < 1V, from Time of VCSN < VBATX - 30mV, VSCHX = TBD, CLOAD = 3nF ILOAD = 1A VGCH1 - VSCH1 VGCH2 - VSCH2 ILOAD =10A VGCH1 - VSCH1 VGCH2 - VSCH2 VCSN - VBATX, 5V VBATX 28V VGCHX - VSCHX = 1.5V
q q
MIN
TYP 5 3
MAX 10 7
UNITS ms s
Charge Mux Switches
5 5 -0.8 -0.8 5 15
5.8 5.8 -0.4 -0.4 20 35 -2 2
7 7 0 0 40 60
V V V V mV mV A A
VCOFF
VTOC VFC IOC(SRC) IOC(SNK) VCHMIN
CH Switch Forward Regulation Voltage VBATX - VCSN, 5V VBATX 28V
3.5
4.7
V
PowerPath Switches tDLY tPPB tONPO tOFFPO VPONO 250 1 5 3 10 7 ms sec s s
4.75 4.75 4.75
6.25 6.25 6.25 0.18 0.18 0.18
7 7 7 0.25 0.25 0.25 60 50
V V V V V V mV mV
VPOFFO
VTOP VFP
5 0
20 25
IOP(SRC) IOP(SNK)
1960f
4
LTC1960
The q denotes specifications which apply over the full operating temperature range (Note 7), otherwise specifications are at TA = 25C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V unless otherwise noted.
SYMBOL tONPI tOFFPI VPONI PARAMETER Gate B1I/B2I/DCI Turn-On Time Gate B1I/B2I/DCI Turn-Off Time Input Gate Clamp Voltage GB1I GB2I GDCI Input Gate Off Voltage GB1I GB2I GDCI SSB/SCK/MOSI Input High/Low Current SSB/MOSI/SCK Input Low Voltage SSB/MOSI/SCK Input High Voltage MISO Output Low Voltage MISO Output Off-State Leakage Current Watch Dog Timer SSB High Time SCK Period SCK High Time SCK Low Time Enable Lead Time Enable Lag Time Input Data Set-Up Time Input Data Hold Time Access Time (From Hi-Z to Data Active on MISO) Disable Time (Hold Time to Hi-Z State on MISO) Output Data Valid Output Data Hold SCK/MOSI/SSB Rise Time SCK/MOSI/SSB Fall Time MISO Fall Time 0.8V to 2V 2V to 0.8V 2V to 0.4V, CL = 200 pF
q q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS VGS < -3V, CLOAD = 3nF (Note 5) VGS > -1V, CLOAD = 3nF (Note 5) ILOAD = 1A Highest (VBAT1 or VSCP) - VGB1I Highest (VBAT2 or VSCP) - VGB2I Highest (VDCIN or VSCP) - VGDCI ILOAD = -25A Highest (VBAT1 or VSCP) - VGB1I Highest (VBAT2 or VSCP) - VGB2I Highest (VDCIN or VSCP) - VGDCI
q q q
MIN
TYP 300 10
MAX
UNITS s s
4.75 4.75 4.75
6.7 6.7 6.7 0.18 0.18 0.18
7.5 7.5 7.5 0.25 0.25 0.25 1 0.8
V V V V V V A V V V A sec ns s ns ns ns ns ns ns
VPOFFI
Logic I/O IIH/IIL VIL VIH VOL IOFF TWD tSSH tCYC tSH tSL tLD tLG tsu tH tA tdis tV tHO tIr tIf tOf -1 2 0.4 2 1.2 680 CLOAD = 200pF RPULLUP = 4.7k on MISO
q
IOL = 1.3mA VMISO = 5V
q q
SPI Timing (See Timing Diagram)
q
2.5
4.5
2 680 680 200 200 100 100 125 125 580 0 250 250 400
ns ns ns ns ns ns ns
CL = 200pF, RPULLUP = 4.7k on MISO
q q
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2. Battery voltage must be adequate to drive gates of PowerPath P-channel FET switches. This does not affect charging voltage of the battery, which can be zero volts. Note 3. See Test Circuit. Note 4. DCIN, BAT1, BAT2 are held at 12V and GDCI, GB1I, GB2I are forced to 10.5V. SCP is set at 12.0V to measure source current at GDCI,
GB1I and GB2I. SCP is set at 11.9V to measure sink current at GDCI, GB1I and GB2I. Note 5. Extrapolated from testing with CL = 50pF. Note 6. VDAC offset is equal to the reference voltage, since VOUT = VREF(16mV * VDAC(VALUE)/2047 + 1). Note 7. The LTC1960C is guaranteed to meet specified performance from 0C to 70C and is designed, characterized and expected to meet specified performance at -40C and 85C, but is not tested at these extended temperature limits.
1960f
5
LTC1960 TYPICAL PERFOR A CE CHARACTERISTICS
Battery Drain Current (BAT1 Selected)
250 240 230
BAT1 CURRENT (A)
TA = 25C
LOAD VOLTAGE (V)
LOAD VOLTAGE (V)
220 210 200 190 180 170 160 150 6 12 24 18 BAT1 VOLTAGE (V) 30
1960 G01
Charger Efficiency
100 90 80
CHARGER OUTPUT (V)
EFFICIENCY (%)
8 6 4 2 0 -0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 TIME (SEC)
1960 G04
60 50 40 30 20 10 0 0 0.025 0.50 0.10 IOUT (A) 2.5 4.0
1960 G14
BAT1 VOLTAGE (V)
70
Charger Load Regulation
12.4
OUTPUT CURRENT ERROR (mA)
12.3 12.2
BAT1 VOLTAGE (V)
CHARGING CURRENT (mA)
12.1 12.0 11.9 11.8 11.7 11.6 0 VIN = 20V VDAC = 12.288V IDAC = 4000mA TA = 25C 1000 2000 3000 CHARGE CURRENT (mA) 4000
1960 G06
6
UW
Power Path Switching
16 15 14 13 12 11 10 9 8 7 6 -50 -40 -30 -20 -10 0 10 20 30 40 50 TIME (s)
1960 G02
Power Path Autonomous Switching
16 15 14 13 12 11 10 9 8 7 NOTE: LIGHT LOAD TO EXAGGERATE SWITCHING EVENT 6 -1 0 2 3 1 TIME (SEC) BAT1 REMOVED
CLOAD = 20F ILOAD = 0.8A TA = 25C
LOPWR THRESHOLD
4
5
1960 G03
Charger Start-Up
12 10
Charger Load Dump
14 12 10 8 6 4 2 0 -4 -2 BAT1 OUTPUT VIN = 20V VDAC = 12.29V IDAC = 3000mA LOAD CURRENT = 1A TA = 25C LOAD CONNECTED LOAD DISCONNECTED 0 2 468 TIME (ms) 10 12 14 16
1960 G05
Charging Current Accuracy
120
500 450 400 350 300 250 200 150 100 50 0
IDAC Low Current Mode vs Normal Mode
VIN = 20V VBAT1 = 12V RSNS = 0.025 TA = 25C
VDCIN = 20V 100 VBAT1 = 12V RSNS = 0.025 T = 25C 80 A 60 40 20 0 -20 -40 0 200 400 600 800 IDAC VALUE 1000 1200
1960 G07
LOW CURRENT MODE NORMAL MODE
0
80 160 240 320 400 480 PROGRAMMED CURRENT (mA)
560
1960 G08
1960f
LTC1960 TYPICAL PERFOR A CE CHARACTERISTICS
Voltage Accuracy
100
OUTPUT VOLTAGE ERROR (mV)
75 50 25 0 -25 -50 -75
DCIN = 24V TA = 25C ILOAD = 100mA BATTERY CURRENT (mA)
BATTERY VOLTAGE (V)
-100 250
450
650 850 1050 VDAC VALUE
Dual vs Sequential Discharge
15 12.0 11.0
BATTERY VOLTAGE (V)
BAT1 VOLTAGE BAT2 VOLTAGE BAT2 VOLTAGE
BATTERY VOLTAGE (V)
10.0 9.0 8.0 12.0 11.0 10.0 9.0 8.0 0 20 40
BAT1 VOLTAGE
BATTERY TYPE: 10.8V Li-Ion(MOLTECH NI2020) LOAD CURRENT = 3A 1960 G12
UW
1250
1960 G09
Dual vs Sequential Charging
3500 3000 2500 2000 1500 1000 500 0 3500 3000 2500 2000 1500 1000 500 0 0 BAT1 CURRENT BAT2 CURRENT SEQUENTIAL 16.0 15.5 15.0 14.5 14.0 13.5 300 17.0 16.5
Dual Charging Batteries with Different Charge State
BAT2 VOLTAGE BAT1 VOLTAGE 3500 3000
BATTERY CURRENT (mA)
2500 2000 1500 BAT1 CURRENT BAT2 CURRENT 0 20 40 60 80 1000 500 0 100 120 140 160 TIME (MINUTES)
BAT1 CURRENT
BAT2 CURRENT
DUAL 100 MINUTES
1450
50
100 150 200 TIME (MINUTES)
250
BATTERY TYPE: 10.8V Li-Ion (MOLTECH NI2020) REQUESTED CURRENT = 3A REQUESTED VOLTAGE = 12.3V MAX CHARGER CURRENT = 4.1A 1960 G10
BAT1 INITIAL CAPACITY = 0% BAT2 INITIAL CAPACITY = 90% PROGRAMMED CHARGER CURRENT = 3A PROGRAMMED CHARGER VOLTAGE = 16.8V
1960 G11
Dual vs Sequential Discharge
14 13 12 11 10 15 14 13 12 11 10 0 20 40 BAT1 VOLTAGE 16 MINUTES 60 80 100 TIME (MINUTES) 120 140 BAT2 VOLTAGE BAT1 VOLTAGE BAT2 VOLTAGE
DUAL
DUAL
SEQUENTIAL
SEQUENTIAL
11 MINUTES
60 80 100 120 140 160 180 TIME (MINUTES)
BATTERY TYPE: 12V NIMH (MOLTECH NJ1020) 1960 G13 LOAD: 33W
1960f
7
LTC1960
PIN FUNCTIONS
Input Power Related
SCN (Pin 4): PowerPath Current Sensing Negative Input. This pin should be connected directly to the "bottom" (output side) of the low valued resistor in series with the three PowerPath switch pairs, for detecting short-circuit current events. Also powers LTC1960 internal circuitry when all other sources are absent. SCP (Pin 5): PowerPath Current Sensing Positive Input. This pin should be connected directly to the "top" (switch side) of the low valued resistor in series with the three PowerPath switch pairs, for detecting short-circuit current events. GDCO (Pin 6): DCIN Output Switch Gate Drive. Together with GDCI, this pin drives the gate of the P-channel switch in series with the DCIN input switch. GDCI (Pin 7): DCIN Input Switch Gate Drive. Together with GDCO, this pin drives the gate of the P-channel switch connected to the DCIN input. GB1O (Pin 8): BAT1 Output Switch Gate Drive. Together with GB1I, this pin drives the gate of the P-channel switch in series with the BAT1 input switch. GB1I (Pin 9): BAT1 Input Switch Gate Drive. Together with GB1O, this pin drives the gate of the P-channel switch connected to the BAT1 input. GB2O (Pin 10): BAT2 Output Switch Gate Drive. Together with GB2I, this pin drives the gate of the P-channel switch in series with the BAT2 input switch. GB2I (Pin 11): BAT2 Input Switch Gate Drive. Together with GB2O, this pin drives the gate of the P-channel switch connected to the BAT2 input. CLP (Pin 24): This is the Positive Input to the Supply Current Limiting Amplifier CL1. The threshold is set at 100mV above the voltage at the DCIN pin. When used to limit supply current, a filter is needed to filter out the switching noise.
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Battery Charging Related
VSET (Pin 13): The Tap Point of a Programmable Resistor Divider which Provides Battery Voltage Feedback to the Charger. A capacitor from CSN to VSET and one from VSET to GND provide necessary compensation and filtering for the voltage loop. ITH (Pin 14): This is the Control Signal of the Inner Loop of the Current Mode PWM. Higher ITH corresponds to higher charging current in normal operation. A capacitor of at least 0.1F to GND filters out PWM ripple. Typical fullscale output current is 30A. Nominal voltage range for this pin is 0V to 2.4V. ISET (Pin 15): A Capacitor from ISET to Ground is Required to Filter Higher Frequency Components from the DeltaSigma IDAC. CSN (Pin 22): Current Amplifier CA1 Input. Connect this to the common output of the charger MUX switches. CSP (Pin 23): Current Amplifier CA1 Input. This pin and the CSN pin measure the voltage across the sense resistor, RSNS, to provide the instantaneous current signals required for both peak and average current mode operation. COMP1 (Pin 25): This is the Compensation Node for the Amplifier CL1. A capacitor is required from this pin to GND if input current amplifier CL1 is used. At input adapter current limit, this node rises to 1V. By forcing COMP1 low, amplifier CL1 will be defeated (no adapter current limit). COMP1 can source 10A. BGATE (Pin 27): Drives the Bottom External MOSFET of the Battery Charger Buck Converter. SW (Pin 30): Connected to Source of Top External MOSFET Switch. Used as reference for top gate driver. BOOST (Pin 31): Supply to Topside Floating Driver. The bootstrap capacitor is returned to this pin. Voltage swing at this pin is from a diode drop below VCC to (DCIN + VCC).
1960f
LTC1960
PIN FUNCTIONS
TGATE (Pin 32): Drives the Top External MOSFET of the Battery Charger Buck Converter. SCH1 (Pin 33), SCH2 (Pin 36): Charger MUX Switch Source Returns. These two pins are connected to the sources of Q3/Q4 and Q9/Q10 (see Typical Application on back page of data sheet), respectively. A small pull-down current source returns these nodes to 0V when the switches are turned off. GCH1 (Pin 34), GCH2 (Pin 35): Charger MUX Switch Gate Drives. These two pins drive the gates of the back-to-back N-channel switch pairs, Q3/Q4 and Q9/Q10, between the charger output and the two batteries. power is considered to be adequate to charge the batteries. If DCDIV is taken more than 1.8V above VCC, then all of the power path switches are latched off until all power is removed. DCIN (Pin 29): Supply. External DC power source. A 1F bypass capacitor should be connected to this pin as close as possible. No series resistance is allowed, since the adapter current limit comparator input is also this pin.
External Power Supply Pins
VPLUS (Pin 1): Supply. The VPLUS pin is connected via four internal diodes to the DCIN, SCN, BAT1, and BAT2 pins. Bypass this pin with a 1F to 2F capacitor. BAT1 (Pin 3), BAT2 (Pin 2): These two pins are the inputs from the two batteries for power to the LTC1960 and to provide voltage feedback to the battery charger. LOPWR (Pin 12): LOPWR Comparator Input from External Resistor Divider Connected from SCN to GND. If the voltage at LOPWR is lower than the LOPWR comparator threshold, then system power has failed and power is autonomously switched to a higher voltage source, if available. See PowerPath section of LTC1960 operation. DCDIV (Pin 17): DCDIV Comparator Input from External Resistor Divider Connected from DCIN to GND. If the voltage at DCDIV is above the DCDIV comparator threshold, then the DC bit is set and the wall adapter
U
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Internal Power Supply Pins
GND (Pin 16): Ground for Low Power Circuitry. PGND (Pin 26): High Current Ground Return for BGATE Driver. VCC (Pin 28): Internal Regulator Output. Bypass this output with at least a 2F to 4.7F capacitor. Do not use this regulator output to supply more than 1mA to external circuitry.
Digital Interface Pins
SSB (Pin 18): SPI Slave Select Input. Active low. TTL levels. This signal is low when clocking data to/from the LTC1960. SCK (Pin 19): Serial SPI Clock. TTL levels. MISO (Pin 20): SPI Master-In-Slave-Out Output, Open Drain. Serial data is transmitted from the LTC1960, when SSB is low, on the falling edge of SCK. TTL levels. A 4.7k pullup resistor is recommended. MOSI (Pin 21): SPI Master-Out-Slave-In Input. Serial data is transmitted to the LTC1960, when SSB is low, on the rising edge of SCK. TTL levels.
1960f
9
LTC1960
BLOCK DIAGRA
DCIN
SCH1 33
ON
SCH2 36 21 MOSI BAT1 BAT2 3 2 CHGMON CHARGE 400k 11 VPLUS 1 SCN 11-BIT VOLTAGE DAC VCC 28 GND 16 DCIN 29 VSET 13 OSCILLATOR BGATE BOOST 31 TGATE 32 SW 30 VCC BGATE 27 PGND 26 DCIN 100mV CLP 24 + CL1 - gm = 0.4m IREV - 40mV + PWM LOGIC Q R CHARGE /15 ICMP LOW DROP DETECT 0.8V TON S + - EA - VCC REGULATOR 0.86V 10-BIT CURRENT DAC 15 ISET CSP-CSN 3k SPI INTERFACE 20 MISO 19 SCK 18 SSB
gm = 1.4m
CA1 - gm = 1.4m +
BUFFERED ITH
CLAMP 25 COMP1 14 ITH
1960 BD
TEST CIRCUIT A D TI I G DIAGRA
Test Circuit
SSB
SPI Timing Diagram
VREF
+
EA
tSSH tLD tCYC tLG
-
CHGMON VSW
SCK
tSH tH tsu tSL
BAT1
BAT2
VSET
ITH
MOSI
BIT 7
+ -
0.5V
1960 TC01
tA MISO SLAVE BIT 7 OUT
tV
10
+
-
+
+
-
-
W
+
UW
+ -
GCH2 35
CSN
0V
CA2
-
SELECTOR CONTROLLER
+
-
GCH1 34
ON
AC_PRESENT
+
-
CHARGE PUMP
SWB1 DRIVER
SWB2 DRIVER
SWDC DRIVER
SHORT CIRCUIT
+
W
GB1I GB1O 9 8 GB2I GB2O 11 10 GDCI GDCO 7 6 100mV 100 4 SCN 17 DCDIV 5 SCP + - 12 LOPWR 1.19V 3k 23 CSP 3k 22 CSN 0.8V
-+
0.75V
CHGMON
U
BIT 0
tHO SLAVE BIT 0 OUT
tdis
1960 TD01
1960f
LTC1960
OPERATIO
OVERVIEW
The LTC1960 is composed of a battery charger controller, charge MUX controller, PowerPath controller, SPI interface, a 10-bit current DAC (IDAC) and 11-bit voltage DAC (VDAC). When coupled with a low cost microprocessor, it forms a complete battery charger/selector system for two batteries. The battery charger is programmed for voltage and current, and the charging battery is selected via the SPI interface. Charging can be accomplished only if the voltage at DCDIV indicates that sufficient voltage is available from the input power source, usually an AC adapter. The charge MUX, which selects the battery to be charged, is capable of charging both batteries simultaneously by selecting both batteries for charging. The charge MUX switch drivers are configured to allow charger current to share between the two batteries and to prevent current from flowing in a reverse direction in the switch. The amount of current that each battery receives will depend upon the relative capacity of each battery and the battery voltage. This can result in significantly shorter charging times (up to 50% for Li-Ion batteries) than sequential charging of each battery. In order to continue charging, the CHARGE_BAT information must be updated more frequently than the internal watchdog timer. The PowerPath controller selects which of the pairs of PFET switches, input and output, will provide power to the system load. The selection is accomplished over the SPI interface. If the system voltage drops below the threshold set by the LOPWR resistor divider, then all of the output side PFETs are turned on quickly and power is taken from the highest voltage source available at the DCIN, BAT1 or BAT2 inputs. The input side PFETs act as diodes in this mode and power is taken from the source with the highest voltage. The input side PowerPath switch driver that is delivering power then closes its input switch to reduce the power dissipation in the PFET bulk diode. In effect, this system provides diode -like behavior from the FET switches, without the attendant high power dissipation from diodes. The microprocessor is informed of this 3-diode mode status when it polls the PowerPath status register via the SPI interface. The microprocessor can then assess which power source is capable of providing power, and program the PowerPath switches accordingly. Since high speed
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(Refer to Block Diagram and Typical Application) PowerPath switching at LOPWR trip points is handled autonomously, there is no need for real-time microprocessor resources to accomplish this task. Simultaneous discharge of both batteries is accomplished by simply programming both batteries for discharge into the system load. The switch drivers prevent reverse current flow in the switches and automatically discharge both batteries into the load, sharing current according to the relative capacity of the batteries. Simultaneous dual discharge can increase battery operating time by approximately 10% by reducing losses in the switches and reducing internal losses associated with high discharge rates. SPI Interface The SPI interface is used to write to the internal PowerPath registers, the charger control registers, the current DAC, and the voltage DAC. The SPI is also able to read internal status registers. There are two types of SPI write commands. The first write command is a 1-byte command used to load PowerPath and charger control bits. The second write command is a 2-byte command used to load the DACs. The SPI read command is a 2-byte command. In order to ensure the integrity of the SPI communication, the last bit received by the SPI is echoed back over the MISO output after the next falling SCK. The data format is set up so that the master has the option of aborting a write if the returned MISO bit is not as expected. 1-Byte SPI Write Format: bit 7........byte 1..........bit 0 MOSI MISO Charger Write Address: Charger Write Data: D0 D1 D2 X A0 A1 A2 0 X D0 D1 D2 X A0 A1 A2 A[2:0] = b111 D2 = X D1 = CHARGE_BAT2 D0 = CHARGE_BAT1
PowerPath Write Address: A[2:0] = b110 PowerPath Write Data: D2 = POWER_BY_DC D1 = POWER_BY_BAT2 D0 = POWER_BY_BAT1
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LTC1960
OPERATIO
2-Byte SPI Write Format: bit 7........byte 1..........bit 0 MOSI MISO IDAC Write Address: IDAC Data Bits D9-D0: IDAC Data Bit D10 : VDAC Write Address: VDAC Data Bits D10-D0: D0 D1 D2 D3 D4 D5 D6 1 X D0 D1 D2 D3 D4 D5 D6 A[2:0] = b000 IDAC value data (MSB-LSB) Normal mode = 0, low current mode = 1 (Dual battery charging is disabled) A[2:0] = b001 VDAC value (MSB-LSB) bit 7..........byte 2............bit 0 D7 D8 D9 D10 A0 A1 A2 0 1 D7 D8 D9 D10 A0 A1 A2
Subsequent SPI communication is inhibited until after the addressed DAC is finished loading. It is recommended that the master transmit all zeros until MISO goes low. This handshaking procedure is illustrated in Figure 1.
SSB BYTE 1 BYTE 2
SCK
MOSI
MISO
1960 F01
2-Byte SPI Read Format: bit 7........byte 1.......bit 0 MOSI MISO Status Address: Status Read Data: 0 0 0 0 A0 A1 A2 0 X 0 0 0 0 A0 A1 A2 A[2:0] = b010 LP = LOW_POWER (Low power comparator output) DC = DCDIV (DCDIV comparator output) PF = POWER_FAIL (Set if selected power supply failed to hold up system power after three tries) CH = CHARGING (One or more batteries are being charged) FA = FAULT. This bit is set for any of the following conditions: 1) The LTC1960 is still in power on reset. 2) The LTC1960 has detected a short circuit and has shut down power and charging. 3) The system has asserted a fast off using DCDIV. Note: All other values of A[2:0] are reserved and must not be used.
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Figure 1. SPI Write to VDAC of Data = b101_0101_0101
bit 7........byte 2............bit 0 0 0 0 0 A0 A1 A2 1 X FA LP DC PF CH X X
LTC1960
OPERATIO
A status read is illustrated in Figure 2.
SSB BYTE 1 BYTE 2
Battery Charger Controller The LTC1960 charger controller uses a constant off-time, current mode step-down architecture. During normal operation, the top MOSFET is turned on each cycle when the oscillator sets the SR latch and turned off when the main current comparator ICMP resets the SR latch. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current reverses, as indicated by current comparator IREV, or the beginning of the next cycle. The oscillator uses the equation: tOFF = 1/fOSC * (VDCIN - VCSN)/VDCIN to set the bottom MOSFET on time. The peak inductor current at which ICMP resets the SR latch is controlled by the voltage on ITH. ITH is in turn controlled by several loops, depending upon the situation at hand. The average current control loop converts the voltage between CSP and CSN to a representative current. Error amp CA2 compares this current against the desired current requested by the IDAC at the ISET pin and adjusts ITH until the IDAC value is satisfied. The BAT1/BAT2 MUX provides the selected battery voltage at CHGMON, which is divided down to the VSET pin by the VDAC resistor divider and is used by error amp EA to decrease ITH if the VSET voltage is above the 0.8V reference. The amplifier CL1 monitors and limits the input current, normally from the AC adapter, to a preset level (100mV/RCL). At input current limit, CL1 will decrease the ITH voltage and thus reduce battery charging current. An overvoltage comparator, 0V, guards against transient overshoots (>7%). In this case, the top MOSFET is turned off until the overvoltage condition is cleared. This feature is useful for batteries which "load dump" themselves by opening their protection switch to perform functions such as calibration or pulse mode charging.
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SCK MOSI MISO
1960 F05
Figure 2. SPI Read of FA = 0, LP = 0, DC = 1, PF = 0, and CH = 1
Charging is inhibited for battery voltages below the minimum charging threshold, VCHMIN. Charging is not inhibited when the low current mode of the IDAC is selected. The top MOSFET driver is powered from a floating bootstrap capacitor CB. This capacitor is normally recharged from VCC through an external diode when the top MOSFET is turned off. A 2F to 4.7F capacitor across VCC to GND is required to provide a low dynamic impedance to charge the boost capacitor. It is also required for stability and power-on-reset purposes. As VIN decreases towards the selected battery voltage, the converter will attempt to turn on the top MOSFET continuously ("dropout''). A dropout timer detects this condition and forces the top MOSFET to turn off, and the bottom MOSFET on, for about 200ns at 40s intervals to recharge the bootstrap capacitor. Charge MUX Switches The equivalent circuit of a charge MUX switch driver is shown in Figure 3. If the charger controller is not enabled, the charge MUX drivers will drive the gate and source of the series connected MOSFETs to a low voltage and the switch is off. When the charger controller is on, the charge MUX driver will keep the MOSFETs off until the voltage at CSN rises at least 35mV above the battery voltage. GCH1 is then driven with an error amplifier EAC until the voltage between BAT1 and CSN satisfies the error amplifier or until GCH1 is clamped by the internal Zener diode. The time required to close the switch could be quite long (many ms) due to the small currents output by the error amp and depending upon the size of the MOSFET switch. If the voltage at CSN decreases below VBAT1 - 20mV a comparator CC quickly turns off the MOSFETs to prevent
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LTC1960
OPERATIO
reverse current from flowing in the switches. In essence, this system performs as a low forward voltage diode. Operation is identical for BAT2.
DCIN + 10V (CHARGE PUMPED) TO BATTERY 1 FROM CHARGER BAT1
CSN
35mV
20mV
Figure 3. Charge MUX Switch Driver Equivalent Circuit
Dual Charging Note that the charge MUX switch drivers will operate together to allow both batteries to be charged simultaneously. If both charge MUX switch drivers are enabled, only the battery with the lowest voltage will be charged until its voltage rises to equal the higher voltage battery. The charge current will then share between the batteries according to the capacity of each battery. If both batteries are selected for charging, only batteries with voltages above VCHMIN are allowed to charge. Dual charging is not allowed when the low current mode of the IDAC is selected. If dual charging is enabled when the IDAC enters low current mode, then only BAT1 will be charged. Charger Start-Up When the charger controller is enabled by the SPI Interface block, the charger output CSN will ramp from 0V until it exceeds the selected battery voltage. The clamp error amp is used to prevent the charger output from exceeding the selected battery voltage by more than 0.7V during the start-up transient while the charge MUX switches, have yet to close. Once the charge MUX switches have closed, the clamp releases ITH to allow control by another loop. PowerPath Controller
The PowerPath switches are turned on and off via the SPI interface, in any combination. The external P-MOSFETs
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-
EAC GCH1 Q3
+
SCH1 CC
+ -
OFF 10k
Q4
1960 F03
are usually connected as an input switch and an output switch. The output switch PFET is connected in series with the input PFET and the positive side of the short-circuit sensing resistor, RSC. The input switch is connected in series between the power source and the output PFET. The PowerPath switch driver equivalent circuit is shown in Figure 4. The output PFET is driven high and low by the output side driver controlling pin GXXO, the PFET is either on or off. The gate of the input PFET is driven by an error amplifier which monitors the voltage between the input power source (BAT1 in this case) and SCP. If the switch is turned off, the two outputs are driven to the higher of the two voltages present across the input/output terminals of the switch. When the switch is instructed to turn on, the output side driver immediately drives the gate of the output PFET approximately 6V below the highest of the voltages present at the input/output. When the output PFET turns on, the voltage at SCP will be pulled up to a diode drop below the source voltage by the bulk diode of the input PFET. If the source voltage is more than 25mV above SCP, EAP will drive the gate of the input PFET low until the input PFET turns on and reduces the voltage across the input/output to the EAP set point, or until the Zener clamp engages to limit the voltage applied to the input PFET. If the source voltage drops more than 20mV below SCP, then comparator CP turns on SWP to quickly prevent large reverse current in the switch. This operation mimics a diode with a low forward voltage drop.
20mV OFF
-
CP
+
FROM BATTERY 1 BAT1 SWP
-
SCP EAP
GB1I Q7
+
25mV GB1O Q8 OFF
RSC TO LOAD CL
1960 F04
Figure 4. PowerPath Driver Equivalent Circuit
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LTC1960
OPERATIO
Autonomous PowerPath Switching The LOPWR comparator monitors the voltage at the load through the resistor divider from pin SCN. If any POWER_BY bit is set and the LOPWR comparator trips, then all of the switches are turned on (3-Diode mode) by the PowerPath controller to ensure that the system is powered from the source with the highest voltage. The PowerPath controller waits approximately 1sec, to allow power to stabilize, and then reverts to the previous PowerPath switch configuration. A power fail counter is incremented to indicate that a failure has occurred. If the power fail counter equals a value of 3, then the PowerPath controller sets the switches to 3-Diode mode and the PF bit is set in the status register. This is a three-strikes-andyou're-out process which is intended to debounce the PowerPath PF indicator. The power fail counter is reset by a power path SPI write. Short-Circuit Protection Short -circuit protection operates in both a current mode and a voltage mode. If the voltage between SCP and SCN exceeds the short-circuit comparator threshold VTSC for more than 15ms, then all of the PowerPath switches are turned off and the FAULT bit (FA) is set. Similarly, if the voltage at SCN falls below 3V for more than 15ms, then all of the PowerPath switches are turned off and the FA bit is set. The FA bit is reset by removing all power sources and allowing the voltage at VPLUS to fall below the UVLO threshold. If the FA bit is set, charging is disabled until VPLUS exceeds the UVLO threshold and charging is requested via the SPI interface. When a hard short-circuit occurs, it might pull all of the power sources down to near 0V potentials. The capacitors on VCC and VPLUS must be large enough to keep the circuit operating correctly during the 15ms short-circuit event. The charger will stop within a few microseconds leaving a small current which must be provided by the capacitor on VPLUS. The recommended minimum values (1F on VPLUS and 2F on VCC, including tolerances) should keep the LTC1960 operating above the UVLO trip voltage long enough to perform the short-circuit function when the input voltages are greater than 8V. Increasing the capacitor across VCC to 4.7F will allow operation down to the recommended 6V minimum.
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Fast PowerPath Turn-Off All of the PowerPath switches can be forced off by setting the DCDIV pin to a voltage between 8V and 10V. This will have the same effect as a short-circuit event. The PF status bit will also be set. DCDIV must be less than 5V and VPLUS must decrease below the UVLO threshold to re-enable the PowerPath switches. Power-Up Strategy All three PowerPath switches are turned on after VPLUS exceeds the UVLO threshold for more than 250ms. This delay is to prevent oscillation from a turn-on transient near the UVLO threshold. The Voltage DAC Block The voltage DAC (VDAC) is a delta-sigma modulator which controls the effective value of an internal resistor, RVSET = 7.2k, used to program the maximum charger voltage. Figure 5 is a simplified diagram of the VDAC operation. The Charger Monitor MUX is connected to the appropriate battery indicated by the CHARGE_BATx bit. The delta-sigma modulator and switch SWV convert the VDAC value, received via SPI communication, to a variable resistance equal to (11/8)RVSET/(VDAC(VALUE)/2047). In regulation, VSET is servo driven to the 0.8V reference voltage, VREF. Therefore programmed voltage is: VBATx = (8/11) VREF 405.3k/7.2k * (VDAC(VALUE)/2047) + VREF = 32,752mV * (VDAC(VALUE)/2047) + 0.8V
BAT1 BAT2 CB2 CSN CB1 VREF RVSET 7.2k SWV VSET CHGMON RVF 405.3k
-
EA
+
TO ITH
MODULATOR
11
DAC VALUE (11 BITS)
1960 F05
Figure 5. Voltage DAC Operation
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LTC1960
OPERATIO
Note that the reference voltage must be subtracted from the VDAC value in order to obtain the correct output voltage. This value is VREF/16mV = 50 (32HEX). Capacitors CB1 and CB2 are used to average the voltage present at the VSET pin as well as provide a zero in the voltage loop to help stability and transient response time to voltage variations. See Applications Information section. The Current DAC Block The current DAC is a delta-sigma modulator which controls the effective value of an internal resistor, RSET = 18.77k, used to program the maximum charger current. Figure 6 is a simplified diagram of the DAC operation. The delta-sigma modulator and switch convert the IDAC value, received via SPI communication, to a variable resistance equal to 1.25RSET/(IDAC(VALUE)/1023). In regulation, ISET is servo driven to the 0.8V reference voltage, VREF, and the current from RSET is matched
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against a current derived from the voltage between pins CSP and CSN. This current is (VCSP - VCSN)/3k. Therefore programmed current is: IAVG = 0.8 VREF 3k/(RSNS RSET) * (IDAC(VALUE)/1023) = (102.3mV/RSNS) * (IDAC(VALUE)/1023) When the low current mode bit (D10) is set to 1, the current DAC enters a different mode of operation. The current DAC output is pulse-width modulated with a high frequency clock having a duty cycle value of 1/8. Therefore, the maximum output current provided by the charger is IMAX/8. The delta-sigma output gates this low duty cycle signal on and off. The delta-sigma shift registers are then clocked at a slower rate, about 40ms/bit, so that the charger has time to settle to the IMAX/8 value. The resulting average charging current is equal to 1/8 of the current programmed in normal mode. Dual battery charging is disabled in low current mode. If both batteries are selected for charging, then only BAT1 will charge.
(VCSP - VCSN) 3k (FROM CA1 AMPLIFIER) ISET CSET RSET 18.77k VREF
+
TO ITH
-
MODULATOR DAC VALUE (10 BITS)
1960 F06
10
Figure 6. Current DAC Operation
AVERAGE CHARGER CURRENT IMAX/8 0 ~ 40ms
1960 F07
Figure 7. Charging Current Waveform in Low Current Mode
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LTC1960
APPLICATIONS INFORMATION
Automatic Current Sharing In a dual parallel charge configuration, the LTC1960 does not actually control the current flowing into each individual battery. The capacity, or Amp-Hour rating, of each battery determines how the charger current is shared. This automatic steering of current is what allows both batteries to reach their full capacity points at the same time. In other words, given all other things equal, charge termination will happen simultaneously. A battery can be modeled as a huge capacitor and hence governed by the same laws. I = C * (dV/dT) where: I = The current flowing through the capacitor C = Capacity rating of battery (using amp-hour values instead of capacitance) dV = Change in voltage dt = Change in time The equivalent model of a set or parallel batteries is a set of parallel capacitors. Since they are in parallel, the change in voltage over change in time is the same for both batteries one and two. dV/dtBAT1 = dV/dtBAT2 From here we can simplify. IBAT1/CBAT1 = dV/dt = IBAT2/CBAT2 IBAT2 = IBAT1 CBAT2/CBAT1 At this point you can see that the current divides as the ratio of the two batteries capacity ratings. The sum of the current into both batteries is the same as the current being supply by the charger. This is independent of the mode of the charger (CC or CV). ICHRG = IBAT1 + IBAT2 From here we solve for the actual current for each battery. IBAT2 = ICHRG CBAT2/(CBAT1 + CBAT2) IBAT1 = ICHRG CBAT1/(CBAT1 + CBAT2) Please note that the actual observed current sharing will vary from manufactures claimed capacity ratings since it
*RCL = 100mV ADAPTER CURRENT LIMIT CL1
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is actual physical capacity rating at the time of charge. Capacity rating will change with age and use and hence the current sharing ratios can change over time. In dual charge mode, the charger uses feedback from the BAT2 input to determine charger output voltage. When charging batteries with significantly different initial states of charge (i.e. one almost full, the other almost depleted), the full battery will get a much lower current. This will cause a voltage difference across the charge MUX switches, which may cause the BAT1 voltage to exceed the programmed voltage. Using MOSFETs in the charge MUX with lower RDS(0N) will alleviate this problem. Adapter Limiting An important feature of the LTC1960 is the ability to automatically adjust charging current to a level which avoids overloading the wall adapter. This allows the product to operate at the same time that batteries are being charged without complex load management algorithms. Additionally, batteries will automatically be charged at the maximum possible rate of which the adapter is capable. This feature is created by sensing total adapter output current and adjusting charging current downward if a preset adapter current limit is exceeded. True analog control is used, with closed loop feedback ensuring that adapter load current remains within limits. Amplifier CL1 in Figure 8 senses the voltage across RCL, connected between the CLP and DCIN pins. When this voltage exceeds 100mV, the amplifier will override programmed charging current to limit adapter current to 100mV/RCL. A lowpass filter formed by 5k and 0.1F is required to eliminate switching noise. If the current limit is not used, CLP should be connected to DCIN.
100mV
- +
+
CLP 0.1F 5k AC ADAPTER INPUT VIN
11960 F08
DCIN
RCL*
+
CIN
Figure 8. Adapter Current Limiting
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LTC1960
APPLICATIONS INFORMATION
Watchdog Timer Charging will begin when either CHARGE_BAT1 or CHARGE_BAT2 bits are set in the charger register (address: 111). Charging will stop if the charger register is not updated prior to the expiration of the watchdog timer. Simply repeating the same data transmission to the charger register at a rate higher than once per second will ensure that charging will continue uninterrupted. Extending System to More than 2 Batteries The LTC1960 can be extended to manage systems with more than 3 sources of power. Contact Linear Technology Applications Engineering for more information. Charging Depleted Batteries Some batteries contain internal protection switches that disconnect a load if the battery voltage falls below what is considered a reasonable minimum. In this case, the charger may not start because the voltage at the battery terminal is less than 5V. The low current mode of the IDAC must be used in this case to condition the battery. In low current mode, there is no minimum voltage requirement (but dual charging is not allowed). Usually, the battery will detect that it is being charged and then close its protection switch, which will allow the IDAC to switch to normal mode. Smart batteries require that charging current not exceed 100mA until valid charging voltage and charging current parameters are transmitted via the SMBus. The low current IDAC mode is ideal for this purpose. Starting Charge with Dissimilar Batteries in Dual Charge Mode When charging batteries of different charger termination voltages, the charger should be started using the following procedure: Step 1. Select only the lowest termination voltage battery for charging, and set the charger to its charging parameters. Step 2. When the battery current is flowing into that battery, change to dual charging mode (without stopping the charger) and set the appropriate charging parameters for this dual charger condition. If this procedure is not followed, and BAT2 is significantly higher voltage than BAT1, the charger could refuse to charge either battery. Charge Termination Issues Batteries with constant-current charging and voltagebased charger termination might experience problems with reductions of charger current caused by adapter limiting. It is recommended that input limiting feature be defeated in such cases. Consult the battery manufacturer for information on how your battery terminates charging. Setting Output Current Limit The full scale output current setting of the IDAC will produce VMAX = 102.3mV between CSP and CSN. To set the full scale current of the DAC simply divide VMAX by RSNS. This is expressed by the following equation: RSNS = 0.1023/IMAX
Table 1. Recommended RSNS Resistor Values
IMAX (A) 1.023 2.046 4.092 8.184 RSNS () 1% 0.100 0.050 0.025 0.012 RSNS (W) 0.25 0.25 0.5 1
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Use resistors with low ESL. Inductor Selection Higher operating frequencies allow the use of smaller inductor and capacitor values. A higher frequency generally results in lower efficiency because of MOSFET gate charge losses. In addition, the effect of inductor value on ripple current and low current operation must also be considered. The inductor ripple current IL decreases with higher frequency and increases with higher VIN. IL = V 1 VOUT 1 - OUT ( f)(L) VIN
Accepting larger values of IL allows the use of low inductances, but results in higher output voltage ripple
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LTC1960
APPLICATIONS INFORMATION
and greater core losses. A reasonable starting point for setting ripple current is IL = 0.4(IMAX). In no case should IL exceed 0.6(IMAX) due to limits imposed by IREV and CA1. Remember the maximum IL occurs at the maximum input voltage. In practice 10H is the lowest value recommended for use. Charger Switching Power MOSFET and Diode Selection Two external power MOSFETs must be selected for use with the LTC1960 charger: An N-channel MOSFET for the top (main) switch and an N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak gate drive levels are set by the VCC voltage. This voltage is typically 5.2V. Consequently, logiclevel threshold MOSFETs must be used. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the "ON" resistance RDS(ON), reverse transfer capacitance CRSS, input voltage and maximum output current. The LTC1960 charger is always operating in continuous mode so the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT/VIN Synchronous Switch Duty Cycle = (VIN - VOUT)/VIN The MOSFET power dissipations at maximum output current are given by: PMAIN = VOUT/VIN(IMAX) 2(1 + )RDS(ON) + k(VIN) 2 (IMAX)(CRSS)(f) PSYNC = (VIN - VOUT)/VIN(IMAX)2(1 + ) RDS(ON) Where is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage or during a short-circuit when the duty cycle in this switch is nearly 100%. The term (1 + ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but = 0.005/C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET characteristics. The constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. If the LTC1960 charger is to operate in low dropout mode or with a high duty cycle greater than 85%, then the topside N-channel efficiency generally improves with a larger MOSFET. Using asymmetrical MOSFETs may achieve cost savings or efficiency gains. The Schottky diode D1, shown in the Typical Application on the back page, conducts during the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. A 1A Schottky is generally a good size for 4A regulators due to the relatively small average current. Larger diodes can result in additional transition losses due to their larger junction capacitance. The diode may be omitted if the efficiency loss can be tolerated. Calculating IC Power Dissipation The power dissipation of the LTC1960 is dependent upon the gate charge of QTG and QBG.(Refer to Typical Application). The gate charge is determined from the manufacturer's data sheet and is dependent upon both the gate voltage swing and the drain voltage swing of the FET. PD = (VDCIN - VVCC)([fOSC(QTG + QBG) + IVCC] + VDCIN * IDCIN) Example: VVCC = 5.2V, VDCIN = 19V, fOSC = 345kHz, QG2 = QG3 = 15nC, IVCC = 0mA. PD = 165mW VSET/ISET Capacitors Capacitor C7 is used to filter the delta-sigma modulation frequency components to a level which is essentially DC. Acceptable voltage ripple at ISET is about 10mVP-P. Since the period of the delta-sigma switch closure, T, is about
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LTC1960
APPLICATIONS INFORMATION
10s and the internal IDAC resistor, RSET, is 18.77k, the ripple voltage can be approximated by:
VISET = VREF * T RSET * C 7
Then the equation to extract C7 is:
C7 =
VREF * T VISET * RSET = 0.8/0.01/18.77k(10s) 0.043F
In order to prevent overshoot during start-up transients the time constant associated with C7 must be shorter than the time constant of C5 at the ITH pin. If C7 is increased to improve ripple rejection, then C5 should be increased proportionally and charger response time to average current variation will degrade. Capacitor CB1 and CB2 are used to filter the VDAC deltasigma modulation frequency components to a level which is essentially DC. CB2 is the primary filter capacitor and CB1 is used to provide a zero in the response to cancel the pole associated with CB2. Acceptable voltage ripple at VSET is about 10mVP-P. Since the period of the delta-sigma switch closure, T, is about 11s and the internal VDAC resistor, RVSET, is 7.2k, the ripple voltage can be approximated by:
VVSET = VREF * T RVSET C B1 || C B2
(
)
Then the equation to extract CB1 || CB2 is:
C B1 || C B2 =
VREF * T RVSET VVSET
CB2 should be 10x to 20x CB1 to divide the ripple voltage present at the charger output. Therefore CB1 = 0.01F and CB2 = 0.1F are good starting values. In order to prevent overshoot during start-up transients the time constant associated with CB2 must be shorter than the time constant of C5 at the ITH pin. If CB2 is increased to improve ripple rejection, then C5 should be increased proportionally and charger response time to voltage variation will degrade.
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Input and Output Capacitors In the 4A Lithium Battery Charger (Typical Application section), the input capacitor (CIN) is assumed to absorb all input switching ripple current in the converter, so it must have adequate ripple current rating. Worst-case RMS ripple current will be equal to one half of output charging current. Actual capacitance value is not critical. Solid tantalum low ESR capacitors have high ripple current rating in a relatively small surface mount package, but caution must be used when tantalum capacitors are used for input or output bypass. High input surge currents can be created when the adapter is hot-plugged to the charger or when a battery is connected to the charger. Solid tantalum capacitors have a known failure mechanism when subjected to very high turn-on surge currents. Only Kemet T495 series of "Surge Robust" low ESR tantalums are rated for high surge conditions such as battery to ground. The relatively high ESR of an aluminum electrolytic for C15, located at the AC adapter input terminal, is helpful in reducing ringing during the hot-plug event. Highest possible voltage rating on the capacitor will minimize problems. Consult with the manufacturer before use. Alternatives include new high capacity ceramic (at least 20F) from Tokin, United Chemi-Con/Marcon, et al. Other alternative capacitors include OSCON capacitors from Sanyo. The output capacitor (COUT) is also assumed to absorb output switching current ripple. The general formula for capacitor current is:
0.29 (VBAT) 1 - IRMS =
For example:
(
VBAT VDCIN
)
(L1)(f)
VDCIN = 19V, VBAT = 12.6V, L1 = 10H, and f = 300kHz, IRMS = 0.41A. EMI considerations usually make it desirable to minimize ripple current in the battery leads, and beads or inductors may be added to increase battery impedance at the 300kHz
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LTC1960
APPLICATIONS INFORMATION
switching frequency. Switching ripple current splits between the battery and the output capacitor depending on the ESR of the output capacitor and the battery impedance. If the ESR of COUT is 0.2 and the battery impedance is raised to 4 with a bead or inductor, only 5% of the current ripple will flow in the battery. Power Path and Charge MUX MOSFET Selection Three pairs of P-channel MOSFETs must be used with the wall adapter and the two battery discharge paths. Two pairs of N-channel MOSFETs must be used with the battery charge path. The nominal gate drive levels are set by the clamp drive voltage of their respective control circuitry. This voltage is typically 6.25V. Consequently, logic-level threshold MOSFETs must be used. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the "ON" resistance RDS(ON), input voltage and maximum output current. For the N-channel charge path, the maximum current is the maximum programmed current to be used. For the P-channel discharge path maximum current typically occurs at end of life of the battery when using only one battery. The upper limit of RDS(ON) value is a function of the actual power dissipation capability of a given MOSFET package that must take into account the PCB layout. As a starting point, without knowing what the PCB dissipation capability would be, derate the package power rating by a factor of two. RDS(ON)MAX = PMOSFET 2 IMAX If you use identical MOSFETs for both battery paths, voltage drops will track over a wide current range. The LTC1960 linear 25mV CV drop regulation will not occur until the current has dropped below:
ILINEARMAX = 25mV 2 RDS(ON)MAX
()
2
If you are using a dual MOSFET package with both MOSFETs in series, you must cut the package power rating in half again and recalculate. RDS(ON)MAX = PMOSFETDUAL 4 IMAX
()
2
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However, if you try to use the above equation to determine RDS(ON) to force linear mode at full current, the MOSFET RDS(ON) value becomes unreasonably low for MOSFETs available at this time. The need for the LTC1960 voltage drop regulation only comes into play for parallel battery configurations that terminate charge or discharge using voltage. At first this seems to be a problem, but there are several factors helping out: 1. When batteries are in parallel current sharing, the current flow through any one battery is less than if it is running stand-alone. 2. Most batteries that charge in constant voltage mode, such as Li-ion, charge terminate at a current value of C/10 or less which is well within the linear operation range of the MOSFETs. 3. Voltage tracking for the discharge process does not need such precise voltage tracking values. The LTC1960 has two transient conditions that force the discharge path P-channel MOSFETs to have two additional parameters to consider. The parameters are gate charge QGATE and single pulse power capability. When the LTC1960 senses a LOW_POWER event, all the P-channel MOSFETs are turned on simultaneously to allow voltage recovery due to a loss of a given power source. However, there is a delay in the time it takes to turn on all the MOSFETs. Slow MOSFETs will require more bulk capacitance to hold up all the system's power supply function during the transition and fast MOSFET will require less bulk capacitance. The transition speed of a MOSFET to an on or off state is a direct function of the MOSFET gate charge. t = QGATE/IDRIVE
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LTC1960
APPLICATIONS INFORMATION
IDRIVE is the fixed drive current into the gate from the LTC1960 and "t" is the time it takes to move that charge to a new state and change the MOSFET conduction mode. Hence time is directly related to QGATE. Since QGATE goes up with MOSFETs of lower RDS(ON), choosing such MOSFETs has a counterproductive increase in gate charge making the MOSFET slower. Please note that the LTC1960 recovery time specification only refers to the time it takes for the voltage to recover to the level just prior to the LOW_POWER event as opposed to full voltage. The single pulse current rating of MOSFET is important when a short-circuit takes place. The MOSFET must survive a 15ms overload. MOSFETs of lower RDS(ON) or MOSFETs that use more powerful thermal packages will have a high power surge rating. Using too small of a pulse rating will allow the MOSFET to blow to the open circuit condition instantly like a fuse. Typically there is no outward sign of failure because it happens so fast. Please measure the surge current for all discharge power paths under worse case conditions and consult the MOSFET data sheet for the limitations. Voltage sources with the highest voltage and the most bulk capacitance are often the biggest risk. Specifically the MOSFETs in the wall adapter path with wall adapters of high voltage, large bulk capacitance and low resistance DC cables between the adapter and device are the most common failures. Remember to only use the real wall adapter with a production DC power cord when performing the wall adapter path test. The use of a laboratory power supply is unrealistic for this test and will force you to over specify the MOSFET ratings. A battery pack usually has enough series resistance to limit the peak current or are too low in voltage to create enough instantaneous power to damage their respective power path MOSFETs.
DIRECTION OF CHARGING CURRENT
VIN CIN
RSNS
1960 F11
1960 F10
CSP
CSN
Figure 10. Kelvin Sensing of Charging Current
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PCB Layout Considerations For maximum efficiency, the switch node rise and fall time is kept as short as possible. To prevent magnetic and electrical field radiation and high frequency resonant problems, proper layout of the components connected to the IC is essential. 1. Keep the highest frequency loop path as small and tight as possible. This includes the bypass capacitors, with the higher frequency capacitors being closer to the noise source than the lower frequency capacitors. The highest frequency switching loop has the highest layout priority. For best results, avoid using vias in this loop and keep the entire high frequency loop on a single external PCB layer. If you must, use multiple vias to keep the impedance down (see Figure 11). 2. Run long power traces in parallel. Best results are achieved if you run each trace on separate PCB layer one on top of the other for maximum capacitance coupling and common mode noise rejection. 3. If possible, use a ground plane under the switcher circuitry to minimize capacitive interplane noise coupling. 4. Keep signal or analog ground separate. Tie this analog ground back to the power supply at the output ground using a single point connection. 5. For best current programming accuracy provide a Kelvin connection from RSENSE to CSP and CSN. See Figure 10 as an example.
SWITCH NODE L1 VBAT HIGH FREQUENCY CIRCULATING PATH
D1
COUT
BAT
Figure 11. High-Speed Switching Path
LTC1960
PACKAGE DESCRIPTIO
5.20 - 5.38** (.205 - .212)
.13 - .22 (.005 - .009)
.55 - .95 (.022 - .037)
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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G Package 36-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
12.67 - 12.93* (.499 - .509) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 7.65 - 7.90 (.301 - .311) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1.73 - 1.99 (.068 - .078) 0 - 8 .65 (.0256) BSC .25 - .38 (.010 - .015) .05 - .21 (.002 - .008)
G36 SSOP 0501
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LTC1960
TYPICAL APPLICATIO
BAT2 BAT1 VIN R1 5.1k 1% VDD 4.7k MISO SCK MOSI SSB R4 14k 1% RCL 0.03 C1 0.1F LTC1960 24 29 3 2 20 19 21 18 17 25 35 36 34 33 13 28 16 CLP DCIN BAT1 BAT2 MISO SCK MOSI SSB DCDIV COMP1 GCH2 SCH2 GCH1 SCH1 VSET VCC GND VPLUS GDCI GDCO GB1I GB1O GB2I GB2O SCP SCN LOPWR CSN CSP ITH ISET SW BOOST TGATE BGATE PGND 1 7 6 9 8 11 10 5 4 12 22 23 14 15 30 31 32 27 26 C4 0.1F L1 10H 4A QBG D1 R6 100 Q4 Q10 RSNS 0.025 1% C6 1F C2 1F
R5 1k 1%
R7 49.9k 1% C3 0.01F
CB2 0.1F
Q1, Q2, Q5, Q6, Q7, Q8: Si4925DY Q3, Q4, Q9, Q10, QTG, QBG: FDS6912A
RELATED PARTS
PART NUMBER LT1505 LTC1628-PG LTC1709 LTC3711 LTC1759 LT1769 DESCRIPTION High Efficiency Battery Charger 2-Phase, Dual Synchronous Step-Down Controller 2-Phase, Dual Synchronous Step-Down Controller with VID No RSENSE Synchronous Step-Down Controller with VID SMBus Controlled Smart Battery Charger 2A Battery Charger COMMENTS Up to 97% Efficiency; AC Adapter Current Limit Minimizes CIN and COUT; Power Good Output; 3.5V VIN 36V Up to 42A Output; Minimum CIN and COUT; Uses Smallest Components for Intel and AMD Processors 3.5V VIN 36V; 0.925V VOUT 2V; for Transmeta, AMD and Intel Mobile Processors Synchronous Operation for High Efficiency; Integrated SMBus Accelerator; AC Adapter Current Limit Constant-Current/Constant-Voltage Switching Regulator; Input Current Limiting Maximizes Charge Current
1960f LT/TP 0202 2K * PRINTED IN USA
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507 q www.linear.com
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Dual Battery Selector & 4A Charger
POWER PATH MUX 100 Q1 C8 0.1F Q2 Q5 Q8 Q6 Q7 RSC 0.02 LOAD CL 20F 25V R9 3.3k 1% C7 0.1F R2 649k 1% R3 100k 1% C5 0.15F QTG D2 C6 2F CB1 0.01F CIN 20F 25V COUT 20F 25V CHARGE MUX Q9 Q3 D1: MBR130T3 D2: IN4148 TYPE
1960 TA02
(c) LINEAR TECHNOLOGY CORPORATION 2001

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